

`define AXI_ADDR_WIDTH      64
`define AXI_DATA_WIDTH      64
`define AXI_ID_WIDTH        4
`define AXI_USER_WIDTH      1

`timescale 1ns / 1ps
module SimTop
(
  input         clock,
  input         reset,
  input  [63:0] io_logCtrl_log_begin,
  input  [63:0] io_logCtrl_log_end,
  input  [63:0] io_logCtrl_log_level,
  input         io_perfInfo_clean,
  input         io_perfInfo_dump,
  output        io_uart_out_valid,
  output [7:0]  io_uart_out_ch,
  output        io_uart_in_valid,
  input  [7:0]  io_uart_in_ch
  // ......
);

    wire aw_ready;
    wire aw_valid;
    wire [`AXI_ADDR_WIDTH-1:0] aw_addr;
    wire [`AXI_ID_WIDTH-1:0] aw_id;
    wire [7:0] aw_len;
    wire [2:0] aw_size;
    wire [1:0] aw_burst;

    wire w_ready;
    wire w_valid;
    wire [`AXI_DATA_WIDTH-1:0] w_data;
    wire [`AXI_DATA_WIDTH/8-1:0] w_strb;
    wire w_last;
    
    wire b_ready;
    wire b_valid;
    wire [1:0] b_resp;
    wire [`AXI_ID_WIDTH-1:0] b_id;
    wire [`AXI_USER_WIDTH-1:0] b_user;

    wire ar_ready;
    wire ar_valid;
    wire [`AXI_ADDR_WIDTH-1:0] ar_addr;
    wire [`AXI_ID_WIDTH-1:0] ar_id;
    wire [7:0] ar_len;
    wire [2:0] ar_size;
    wire [1:0] ar_burst;
    
    wire r_ready;
    wire r_valid;
    wire [1:0] r_resp;
    wire [`AXI_DATA_WIDTH-1:0] r_data;
    wire r_last;
    wire [`AXI_ID_WIDTH-1:0] r_id;
/********** 输出信号 **********/
wire 					sram_ren;
wire  [3:0]			sram_arsize;
wire  [31:0]			sram_araddr;
reg [63:0]			sram_rdata;
wire 					sram_wen;
wire  [3:0]			sram_awsize;
wire  [31:0]			sram_awaddr;
wire  [63:0]			sram_wdata;
reg [63:0]wmask_interm;
wire [63:0]wmask;
assign wmask=wmask_interm<<(8*sram_awaddr[2:0]);
always@(*)
    case(sram_awsize)
        4'b0000:wmask_interm=64'h0000_0000_0000_000F;
        4'b0001:wmask_interm=64'h0000_0000_0000_00FF;
        4'b0010:wmask_interm=64'h0000_0000_0000_FFFF;
        4'b0011:wmask_interm=64'h0000_0000_FFFF_FFFF;
        4'b0100:wmask_interm=64'hFFFF_FFFF_FFFF_FFFF;
        default:wmask_interm=64'h0000_0000_0000_0000;
    endcase
always @(posedge clock)
begin
    if(sram_ren)
        sram_rdata<=ram_read_helper(1'b1, (sram_araddr>>3));//{memcore[{sram_araddr[21:3],1'b1}],memcore[{sram_araddr[21:3],1'b0}]}
    else
        sram_rdata<=sram_rdata;
    
    if(sram_wen)
        ram_write_helper((sram_awaddr-32'h8000_0000)>>3,sram_wdata,wmask,1'b1);
end





ysyx_210152_Vostok564_top DUT(
//----------------------Global signal---------------------
    .clock(clock),   //Core clock (PRV564 kernal's clock)
    .reset(reset),   //Core reset(), async
//-----------------------AXI interface---------------------
    .io_master_awid(aw_id),
    .io_master_awaddr(aw_addr),
    .io_master_awlen(aw_len),
    .io_master_awsize(aw_size),
    .io_master_awburst(aw_burst),
    .io_master_awvalid(aw_valid),
    .io_master_awready(aw_ready),
//---------------------写数据通道-----------------------------
    .io_master_wdata(w_data),
    .io_master_wstrb(w_strb),
    .io_master_wlast(w_last),
    .io_master_wvalid(w_valid),
    .io_master_wready(w_ready),
//----------------------写回复通道-------------------------------	
    .io_master_bid(b_id),
    .io_master_bresp(b_resp),
    .io_master_bvalid(b_valid),
    .io_master_bready(b_ready),
//---------------------读地址通道-----------------------------------	
    .io_master_arid(ar_id),
    .io_master_araddr(ar_addr),
    .io_master_arlen(ar_len),
    .io_master_arsize(ar_size),
    .io_master_arburst(ar_burst),
    .io_master_arvalid(ar_valid),
    .io_master_arready(ar_ready),
//----------------------读数据通道----------------------------------
    .io_master_rid(r_id),
    .io_master_rdata(r_data),
    .io_master_rresp(r_resp),
    .io_master_rlast(r_last),
    .io_master_rvalid(r_valid),
    .io_master_rready(r_ready),
    .io_interrupt(1'b0)
);





axi_slave_if#(  .DATA_WIDTH(64),             //数据位宽
            .ADDR_WIDTH(32),               //地址位宽              
            .ID_WIDTH  (4),               //ID位宽
            .USER_WIDTH(1)             //USER位宽
)TEST_RAM_INTERPRETER(            
    .ACLK(clock),              
    .ARESETn(!reset),
    .AWID(aw_id),
    .AWADDR(aw_addr),
    .AWLEN(aw_len),
    .AWSIZE(aw_size),
    .AWBURST(aw_burst),
    .AWVALID(aw_valid),
    // 	output    	                
    .AWREADY(aw_ready),
    .WDATA(w_data),
    .WSTRB(w_strb),          
    .WLAST(w_last),          
    .WVALID(w_valid),       
    .WREADY(w_ready),
    .BID(b_id),
    .BRESP(b_resp),
    .BVALID(b_valid),
    .BREADY(b_ready),
    .ARID(ar_id),
    .ARADDR(ar_addr),     
    .ARLEN(ar_len),        
    .ARSIZE(ar_size),        
    .ARBURST(ar_burst),          
    .ARVALID(ar_valid),    
    .ARREADY(ar_ready),
    .RID(r_id),
    .RDATA(r_data),        
    .RRESP(r_resp),                
    .RLAST(r_last),                  
    .RVALID(r_valid),             
    .RREADY(r_ready),    
    .sram_rdata(sram_rdata),		
    .ren(sram_ren),	
    .arsize(sram_arsize),	
    .araddr(sram_araddr),
    .wen(sram_wen),	
    .awsize(sram_awsize),		
    .awaddr(sram_awaddr),
    .wdata(sram_wdata)
);  
endmodule
